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master spi的源代码（verilog），包括文档，测试程序-master spi the source code (verilog), including documentation, testing procedures
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SPI master的verilog代码-Verilog code for SPI master
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SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
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用FPGA实现主SPI程序,包含开发工程、测试文件和源文件代码-fpga design the SPI code
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SPI总线Master的verilog代码-SPI Bus Master of Verilog code
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This is a verilog code used oversampled
clock to implement SPI slave. Also include C code for a ARM processor
as the SPI master-This is a verilog code used oversampled
clock to implement SPI slave
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实现SPI MASTER功能，并有仿真代码和仿真结果。-To achieve SPI MASTER function, and a simulation code and simulation results.
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This a verilog code for SPI Master testbench is also provided
spi_top.v
Xilinx ISE or Icarus verilog to compile and simulate-This is a verilog code for SPI Master testbench is also provided
spi_top.v
Xilinx ISE or Icarus verilog to compile an
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此代码是SPI接口的Master的Verilog源代码，经上板测试是没有问题的，请大家放心使用-This code SPI Interface Master of Verilog source code, there is no problem on board test, please rest assured to use
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SPI master verilog code
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spi master code for fpga quartus altera
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本源码是用verilog语言编写的FPGA的SPI主机代码，可以用做SPI开发参考。-The source code is written in verilog FPGA SPI master code, can be used to develop a reference SPI.
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有关Verilog的SPI通信的代码,可以应用于FPGA的通信-this is verilog code about SPI
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SPI master 的verilog源码，具有很好的学习价值。-Master SPI Verilog source code, has a good learning value.
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It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.-It is a Verilog code for SPI master. It includes source code and a testbench to test the functionality.
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SPI Interface Master Control RTL Verilog Code
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verilog SPI 读写时序，测试验证OK.-SPI Verilog Code, Master and Slaver.
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code for Master side
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Use code for Maser SPI
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spi 的verilog rtl 代码, 包括整体仿真环境，测试码等(spi master or slave verilog rtl code)
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